Reference is made to FIG. 1 which illustrates a block diagram of a conventional electronic circuit 10 configured to implement gain and offset compensation. The circuit 10 may, for example, receive an input signal (In) and generate an output signal (Out). The circuit 10 is powered from a power supply coupled to a first power supply node 12 and second power supply node 14. In an embodiment, the power supply may be configured to supply a Vdd supply voltage to node 12 and a ground supply voltage to node 14. The circuit 10 may comprise any type of electronic circuit or component which performs a signal amplification operation. Examples of such circuits include, without limitation, signal amplifiers, converters (such as analog-to-digital), and the like, which may include digital circuitry, analog circuitry and mixed analog-digital circuitry.
Those skilled in the art understand that the electronic circuit 10 and, more particularly, the circuit components thereof, do not exhibit an ideal operation. Indeed, voltage gain and voltage offset errors are often present. To account for this fact, the circuit designer includes compensation circuitry. At a nominal supply voltage condition and a nominal temperature environment condition, the compensation circuitry is designed to compensate for first order systematic errors in gain and voltage. For example, gain compensation can be provided to adjust the operation of a controllable gain element 22 within the circuit 10 by specifying a gain error (referred to as “Gf”). Additionally, voltage compensation can be provided adjust the operation of the controllable gain element 22 within the circuit 10 by specifying a voltage offset error (referred to as “Of”).
The controllable gain element 22 receives an input signal (Ir) that may, for example, be derived from the signal In, and generates an output signal (Ic) that may, for example, be used to derive the output signal Out. From a schematic perspective, the controllable gain element 22 includes a gain device 30 and a summing device 32 (implemented in the digital domain, analog domain, or mixed signal domain). A gain error circuit 20 stores the gain error (Gf) which is applied to the gain device 30 to specify a gain applied to the input signal Ir. An offset error circuit 24 stores the voltage offset error (Of) which is applied to the summing device 32 to specify a voltage offset applied to the gain adjusted signal generated by the gain device 30. This compensation operation implemented in connection with operation of the controllable gain element 22 may be mathematically represented by the following formula: Ic=(Ir*Gf)+Of.
Those skilled in the art understand that the error circuits 20 and 24 can be structurally implemented in a number of different ways. In one embodiment, trim circuitry is provided which generates output signals specifying the values of each error. In another embodiment, programmable registers are provided which generate output signals specifying the values of each error. In either case, the controllable gain element 22 is operable responsive to the generated error output signals to effectuate first order error compensation relative to the nominal supply voltage condition and the nominal temperature environment condition.
The foregoing compensation technique is well suited to address first order systematic errors at nominal operating conditions. As the supply voltage and environmental temperature change in the course of circuit 10 operation, those skilled in the art understand that second order errors arise which are not addressed and corrected by the error circuits 20 and 24. These second order errors may go uncorrected in prior art circuitry.
There is accordingly a need in the art to provide for automated gain and offset compensation which accounts for variation in supply voltage and environmental temperature during circuit operation.